Cycle-Accurate Macro-Models for RT-Level Power Analysis - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
نویسندگان
چکیده
In this paper, we present a methodology and techniques for generating cycle-accurate macro-models for registertransfer (RT)-level power analysis. The proposed macro-model predicts not only the cycle-by-cycle power consumption of a module, but also the moving average of power consumption and the power profile of the module over time. We propose an exact power function and approximation steps to generate our power macro-model. First-order temporal correlations and spatial correlations of up to order three are considered in order to improve the estimation accuracy. A variable reduction algorithm is designed to eliminate the “insignificant” variables using a statistical sensitivity test. Population stratification is employed to increase the model fidelity. Experimental results show our macromodels with 15 or fewer variables, exhibit <5% error for average power and <20% errors for cycle-by-cycle power estimation compared to circuit simulation results using Powermill.
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